By Himanshu Bhatnagar
The emphasis of this ebook is on real-time program of Synopsys instruments, used to wrestle numerous difficulties obvious at VDSM geometries. Readers could be uncovered to a good layout technique for dealing with complicated, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties similar to every section of the layout circulation are pointed out, with suggestions and work-around defined intimately. moreover, the most important matters comparable to structure, including clock tree synthesis and back-end integration (links to format) also are mentioned at size. in addition, the publication includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding types, precise in the direction of optimum synthesis resolution.
goal audiences for this booklet are training ASIC layout engineers and masters point scholars venture complex VLSI classes on ASIC chip layout and DFT techniques.
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Additional resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime®
Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ Physical Compiler™ and PrimeTime® by Himanshu Bhatnagar